DocumentCode
3149108
Title
A Technology Independent MOS Multiplier Generator
Author
Chu, Kung-chao ; Sharma, Ramautar
Author_Institution
Bell Laboratories, Murray Hill, NJ
fYear
1984
fDate
25-27 June 1984
Firstpage
90
Lastpage
97
Abstract
A layout generator for technology independent implementation of the MOS multiplier is described. The modified Booth´s algorithm with a structured floor plan has been used. The layout has been optimized and described as a program in a high level layout language. The fabrication process related information is maintained in a separate technology database that is coupled with the layout program at the time of execution to generate the mask data. The user can choose from a variety of architectures for speed, area, and power trade-off´s. The user can also specify geometric and electrical constraints tailored to his system specification.
Keywords
Adders; Circuit synthesis; Encoding; Fabrication; Integrated circuit interconnections; Logic arrays; Registers; Signal generators; Spatial databases; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585779
Filename
1585779
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