Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems

Author

Goel, Manish ; Shanbhag, Naresh R.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

8-10 Oct 1998

Firstpage

317

Lastpage

326

Abstract

We present low-power equalizers derived via dynamic algorithm transformations (DAT). These transformations achieve low-energy operation by reconfiguring the architecture and the supply voltage in response to channel non-stationarities. Practical reconfiguration strategies are derived as a solution to an optimization problem with energy as the objective function and a constraint on the algorithm performance (specifically the SNR). Simple energy models for multipliers are presented. The DAT-based adaptive filter is employed as an equalizer for 51.84 Mbit/s very high-speed digital subscriber loop (VDSL) over 24-pair BKMA cable. On average, 88% energy savings are achieved due to variations in cable length and number of far-end crosstalk (FEXT) interferers

Keywords

adaptive equalisers; adaptive filters; circuit optimisation; digital subscriber lines; modems; reconfigurable architectures; 24-pair BKMA cable; 51.84 Mbit/s; SNR; VDSL; adaptive filter; channel non-stationarities; dynamic algorithm transformations; far-end crosstalk interferers; low-power equalizers; modems; multipliers; optimization; performance; reconfigurable architecture; supply voltage; very-high-speed digital subscriber loop; Adaptive filters; Constraint optimization; Crosstalk; DSL; Equalizers; Finite impulse response filter; Hardware; Heuristic algorithms; Modems; Signal processing algorithms; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on

Conference_Location

Cambridge, MA

ISSN

1520-6130

Print_ISBN

0-7803-4997-0

Type

conf

DOI

10.1109/SIPS.1998.715794

Filename

715794