DocumentCode
3149289
Title
Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology
Author
Sorsch, T. ; Timp, W. ; Baumann, F.H. ; Bogart, K.H.A. ; Boone, T. ; Donnelly, V.M. ; Green, M. ; Evans-Lutterodt, K. ; Kim, C.Y. ; Moccio, S. ; Rosamilia, J. ; Sapjeta, J. ; Silvermann, P. ; Weir, B. ; Timp, G.
Author_Institution
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
fYear
1998
fDate
9-11 June 1998
Firstpage
222
Lastpage
223
Abstract
We report our assessment of the limitation imposed by the tunneling current density on the scaling of stoichiometric oxides grown by rapid thermal oxidation at 1000/spl deg/C over thicknesses ranging from 0.5-3 nm.
Keywords
MOSFET; current density; dielectric thin films; oxidation; rapid thermal processing; tunnelling; 1.0 to 3.0 nm; 1000 degC; MOS technology; SiO; high performance sub-100 nm technology; rapid thermal oxidation; stoichiometric oxides; tunneling current density; ultra-thin gate oxides; Leakage current; MOSFET circuits; Optical films; Oxidation; Reflectivity; Rough surfaces; Surface roughness; Surface treatment; Thickness measurement; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4770-6
Type
conf
DOI
10.1109/VLSIT.1998.689265
Filename
689265
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