DocumentCode
3149411
Title
Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI
Author
DasGupta, S. ; Graf, M.C. ; Rasmussen, R.A. ; Walther, R.G. ; Williams, T.W.
Author_Institution
IBM Corporation, Poughkeepsie, NY
fYear
1984
fDate
25-27 June 1984
Firstpage
203
Lastpage
208
Abstract
This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.
Keywords
Control systems; Cost function; Feeds; Large scale integration; Latches; Logic testing; Packaging; Shift registers; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585795
Filename
1585795
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