Title :
A Systolic Design Rule Checker
Author :
Kane, RaJiv ; Sahni, Sartaj
Author_Institution :
University of Minnesota
Abstract :
We develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design.
Keywords :
Design Rule Checks; feature width; rectilinear geometries; spacing; systolic systems; Algorithm design and analysis; Chip scale packaging; Circuits; Complexity theory; Computer architecture; Design automation; Geometry; Logic; Routing; Wire; Design Rule Checks; feature width; rectilinear geometries; spacing; systolic systems;
Conference_Titel :
Design Automation, 1984. 21st Conference on
Print_ISBN :
0-8186-0542-1
DOI :
10.1109/DAC.1984.1585802
