Title :
Analysis on the design process of CMOS LNA with ESD protection circuit and package PAD
Author :
Chen, Peng ; Zhang, Yonghu
Author_Institution :
Satellite Navig. & Positioning R&D Center, Nat. Univ. of Defense Technol., Changsha, China
Abstract :
A low noise amplifier(LNA) working at GPS L1 band was designed using TSMC 0.18 μm CMOS process with inductively source-degeneration cascode topology. The design process was given firstly and then improved after considering the parasitics resulting from ESD protection circuit and package PAD. Simulation results show that the parasitic effects coming from ESD protection circuit and package PAD should be taken into consideration in the design process.
Keywords :
CMOS integrated circuits; electrostatic discharge; low noise amplifiers; network topology; CMOS LNA; ESD protection circuit; inductively source-degeneration cascode topology; low noise amplifier; package PAD; CMOS integrated circuits; Electrostatic discharge; Europe; Global Positioning System; Low-noise amplifiers; Noise; Publishing; CMOS; Cascode; ESD; GPS; Low noise amplifier(LNA); Package PAD; Parasitics;
Conference_Titel :
Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
Conference_Location :
XianNing
Print_ISBN :
978-1-61284-458-9
DOI :
10.1109/CECNET.2011.5768327
