Digital demodulator matching on a FPGA

Author

Boutillon, Emmanuel ; Danger, Jean-Luc ; Fonséca, Lucie ; García, Andres ; González, Luis

Author_Institution

Ecole Nat. Superieure des Telecommun., Paris, France

fYear

1998

fDate

8-10 Oct 1998

Firstpage

366

Lastpage

375

Abstract

We present a digital demodulator based on a FPGA design. After the presentation of the demodulator algorithm, we describe its integration on a programmable logic device (ALTERA FLEX10K100). We focus on how the FPGA characteristics can change the expertise of the designer at all levels of the design flow, from bit level to algorithm level and methodology level

Keywords

demodulators; digital signal processing chips; field programmable gate arrays; ALTERA FLEX10K100; FPGA; digital demodulator matching; programmable logic device; Algorithm design and analysis; Application specific integrated circuits; Decoding; Delay effects; Demodulation; Design optimization; Fabrication; Field programmable gate arrays; Frequency; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on

Conference_Location

Cambridge, MA

ISSN

1520-6130

Print_ISBN

0-7803-4997-0

Type

conf

DOI

10.1109/SIPS.1998.715799

Filename

715799

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3150296