Title :
Cycle-efficient lineary feedback shift register implementation on word-based micro-architecture
Author :
Lin, Jui-Chieh ; Chen, Sao-Jie ; Hu, Yu Hen
Author_Institution :
Dept. Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA
Abstract :
A novel algorithm transformation method, called term-preserving look-ahead transformation (TePLAT) is proposed to transform the bit-serial linear feedback shift register (LFSR) algorithm into a bit-parallel formulation which promises order of magnitudes improvement of execution speed compared to the traditional look-ahead algorithm transformation approach. TePLAT is applied to 26 commonly used LFSRs and tested on two popular word-based micro-processor development platforms: a Texas Instrument C6416 Code Composition Simulator and an ARM-9 Simulator. In all 26 cases, TePLAT transformed implementations consistently deliver much higher throughput than those implementations based on traditional look-ahead algorithm transformation.
Keywords :
circuit feedback; microcontrollers; microprocessor chips; shift registers; ARM-9 simulator; LFSR algorithm; TePLAT; Texas instrument C6416 code composition simulator; bit-parallel formulation; bit-serial linear feedback shift register algorithm; cycle-efficient lineary feedback shift register; look-ahead algorithm transformation approach; term-preserving look-ahead transformation; word-based microarchitecture; word-based microprocessor development platforms; Generators; Linear feedback shift registers; Parallel processing; Polynomials; Program processors; Throughput; Vectors; Linear feedback shift register; iteration bound; look ahead transformation; scrambler; vector processing;
Conference_Titel :
Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-0045-2
Electronic_ISBN :
1520-6149
DOI :
10.1109/ICASSP.2012.6288203
