Hierarchical Layout Verification

As custom designs approach one million transistor complexity, more emphasis must be placed on hierarchical verification and synthesis tools. This paper describes a hierarchical layout verification system that includes schematic to layout netlist comparison and design rule checking. A hierarchical cell structure definition is presented along with some of the restrictions deemed necessary for a practical implementation. A method for oversizing and undersizing geometries in the context of this hierarchical cell structure, and some of the ramifications of hierarchical design are also discussed.