Title :
Delay and Power Optimization in VLSI Circuits
Author :
Glasser, Lance A. ; Hoyte, Lennox P J
Author_Institution :
Electrical Engineering and Computer Science Department and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
Abstract :
The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.
Keywords :
Circuit optimization; Delay; Laboratories; Large scale integration; MOS devices; Macrocell networks; Power engineering computing; Programmable logic arrays; Silicon; Very large scale integration;
Conference_Titel :
Design Automation, 1984. 21st Conference on
Print_ISBN :
0-8186-0542-1
DOI :
10.1109/DAC.1984.1585848
