DocumentCode
3150435
Title
IDA: Interconnect Delay Analysis for Integrated Circuits
Author
de Geus, A.J. ; Reed, J.B. ; Rekhson, M. ; Wikle, G.
Author_Institution
General Electric Microelectronics Center, Research Triangle Park, NC
fYear
1984
fDate
25-27 June 1984
Firstpage
536
Lastpage
541
Abstract
A delay analysis program has been developed to compute the signal propagation delays attributed to RC interconnection nets in integrated circuits. To take into account the bidirectional nature of MOS transmission gates, the program simulates nets connected through transmission gates as single entities refered to as "supernets". In order to obtain a single set of realistic lumped delays for nets with transmission gates, a delay path analysis and reduction algorithm is used.
Keywords
Adders; Capacitance; Circuit analysis; Circuit simulation; Computational modeling; Electric resistance; Integrated circuit interconnections; Performance analysis; Propagation delay; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585849
Filename
1585849
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