On using address scrambling to implement defect tolerance in SRAMs

This paper proposes an innovative approach to cope with defects in SRAM bit-cell array. Traditional approaches use spare parts (rows, columns or blocks) to replace defective bit-cells. Instead of replacing defective bit-cells, we propose to operate the SRAM with reduced storage capacity whenever defective bit-cells are present. We implement this feature through a programmable combinational logic, called Scrambling Module (SM), which scrambles the memory addresses. The scrambling changes the addresses of the defective bit-cells, grouping them in an idle address zone located at the end of the memory address plan. The SM is described by using a mathematical formulation based on linear algebra. The proposed technique can be used in combination with traditional redundancy approaches using spare rows and/or columns. The effectiveness of three different SM is demonstrated, considering a 1MBit SRAM. For a given level of defect tolerance, it is shown that our technique can reduce the amount of spare area by several orders of magnitude. Moreover, as the SM is implemented as an external block, it does not affect the maximum operation frequency of the SRAM. Instead, it affects the memory access delay.