Lithography aware critical area estimation and yield analysis

Advancing technology nodes have increased the impact of lithography variation on design yield and performance. Although lithographic distortion is emerging as the dominant mode of failure, particulate defect still remains an important source of defect. In this work, we present a novel critical area analysis technique that deals with non-deterministic line edges that arise due to statistical lithography variations. Previous critical area analysis techniques are based on fixed printed structures with variable defect sizes. The proposed solution integrates lithographic variations within critical area analysis, using available tools while keeping the computational complexity in check. The key optimizations include weighted stratified sampling of important lithographic parameters and Monte Carlo based Probability of Failure (POF) calculation that is scalable to large chips. Simulation results on ISCAS benchmarks show that inclusion of lithography induced physical variations can increase critical area by as much as 2X, while overall yield due to particulate defects in large designs may decrease by more than 5%; validating both the need for an integrated solution and its feasibility on large designs.