DocumentCode :
3151878
Title :
ALLENDE: A Procedural Language for the Hierarchical Specification of VLSI Layouts
Author :
Mata, José Monteiro da
Author_Institution :
Department of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ and Departamento de Ciencia da Computacao, Universidade Federal de Minas Gerais, Belo Horizonte, MG, BRASIL
fYear :
1985
fDate :
23-26 June 1985
Firstpage :
183
Lastpage :
189
Abstract :
ALLENDE is a simple and powerful procedural language for VLSI layout. In ALLENDE the layout is described hierarchically as a composition of cells; absolute sizes or positions are never specified. The layout description is translated into linear constraints, which express design rules and relative position of the layout elements. By solving these constraints we obtain the absolute layout, which is guaranteed to be free of design rule violations. Errors in the layout description are immediately detected and easily located. ALLENDE consists of five procedures to be called from a Pascal or C program. A lot of parameterization is possible when specifying layout elements, besides the ability to make use of the full power of Pascal or C. The ALLENDE system has been implemented for the nMOS technology.
Keywords :
Circuit topology; Design automation; Layout; MOS devices; Power engineering computing; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1985. 22nd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0635-5
Type :
conf
DOI :
10.1109/DAC.1985.1585933
Filename :
1585933
Link To Document :
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