Test clock domain optimization for peak power supply noise reduction during scan

Author

Wen, Jen-Yang ; Huang, Yu-Chuan ; Tsai, Min-Hong ; Liao, Kuan-Yu ; Li, James C -M ; Chang, Ming-Tung ; Tsai, Min-Hsiu ; Tseng, Chih-Mou ; Li, Hung-Chun

Author_Institution

Lab. of Dependable Syst., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2011

fDate

20-22 Sept. 2011

Firstpage

1

Lastpage

8

Abstract

This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.

Keywords

circuit noise; circuit optimisation; circuit testing; clocks; design for testability; flip-flops; power supply circuits; DfT technique; IR drop simulation tool; benchmark circuits; design for testability technique; half million gate design; maximum flip-flop density; partition technique; peak power supply noise reduction; scan chain shifting; test clock domain optimization; time 14 min; time 3 hour; Automatic test pattern generation; Benchmark testing; Clocks; Flip-flops; Logic gates; Optimization; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2011 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Print_ISBN

978-1-4577-0153-5

Type

conf

DOI

10.1109/TEST.2011.6139163

Filename

6139163