Title :
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan
Author :
Sunter, Stephen ; Roy, Aubin
Author_Institution :
Mentor Graphics, Ottawa, ON, Canada
Abstract :
An I/O BIST with calibrated 50 ps delay measurement resolution, presented at ITC´10, requires no changes to 1149.1 boundary scan cells nor the I/O cells they access, and avoids using delay cells or delay matching. In this paper, we describe how we improved the silicon-proven resolution by 10X (to 5 ps) without limiting the delay range. The finer resolution enables measurement of crosstalk between I/Os, which is a known source of jitter - we provide results measured on an FPGA. We also describe three new tests (for duty cycle, slew rate, and skew) that unobtrusively test I/O parameters while high-speed data from core logic is being transmitted on DDR pins (or USB2). Lastly, we describe how adaptive test limits are applied by setting limits on-chip relative to the average value measured for any selected group of pins on each device.
Keywords :
boundary scan testing; built-in self test; field programmable gate arrays; DDR pins; FPGA; adaptive parametric BIST; boundary scan; duty cycle test; high speed parallel I/O; skew test; slew rate test; Built-in self-test; Clocks; Delay; Latches; Pins; Radiation detectors; DDR; I/O BIST; delay measurement; high-speed I/O;
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-0153-5
DOI :
10.1109/TEST.2011.6139165
