Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
Intermediate results in digital signal processing (DSP) hardware frequently must be truncated or rounded to maintain reasonable wordlengths. Noise and bias are introduced into the signal due to these operations. For the addition operation, we introduce and investigate two methods which reduce variance and bias and yet maintain the computational simplicity of truncation. Essentially, each method drives the least significant carry input of the adder string with a very simple Boolean function. We demonstrate the utility of these approaches by calculating bias and variance reductions, and by using the methods in several simple but important DSP examples
Keywords :
Boolean functions; digital arithmetic; digital signal processing chips; roundoff errors; Boolean function; DSP; adder string; bias reduction; computational simplicity; digital signal processing; lazy rounding; least significant carry input; truncation; variance reduction; wordlengths; Arithmetic; Boolean functions; Digital signal processing; Field programmable gate arrays; Hardware; Random variables; Signal design; Signal processing; Signal processing algorithms; System performance;
Conference_Titel :
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4997-0
DOI :
10.1109/SIPS.1998.715807