DocumentCode
3152086
Title
Test access and the testability features of the Poulson multi-core Intel Itanium® processor
Author
Bhavsar, Dilip K. ; Poehlman, Steve J.
fYear
2011
fDate
20-22 Sept. 2011
Firstpage
1
Lastpage
8
Abstract
This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel´s latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.
Keywords
innovation management; multiprocessing systems; program debugging; testing; Poulson multicore Intel Itanium processor; debug platform; innovative solution; manufacturing test; multicore CPU testing; scalable test access mechanism design; t-ring based DFX access architecture; test access; testability feature; Arrays; Bandwidth; Clocks; Discrete Fourier transforms; Pins; Registers; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2011 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Print_ISBN
978-1-4577-0153-5
Type
conf
DOI
10.1109/TEST.2011.6139168
Filename
6139168
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