An analog VLSI front-end for auditory signal analysis

Several researchers have found that signal processing of speech based on the principles of the human auditory system leads to noise-robust speech recognition systems. However it is impractical to implement such signal processing algorithms on a general-purpose digital computer, due to the enormous computational complexity of these algorithms. Therefore, we have implemented an auditory-signal processing system using low-power real-time analog and mixed-mode circuits. This implementation attempts to minimize the potential device-mismatch limitations, that can affect the performance of the final speech recognition system. The analog VLSI chip will serve as the front-end of a speech-recognition system. The chip architecture is inspired by biological auditory models common to humans and primate vertebrates. We include experimental results for a 1.2 μm CMOS prototype. We also include speech recognition results obtained from software simulations of the hardware on the TI-DIGITS database, in which we have used linear discriminant analysis to reduce the feature dimension, and to interface the auditory-features to hidden Markov models