A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores

This paper introduces a novel Test Access Mechanism (TAM) for chips with multiple isolated identical cores through which all the cores can be tested in parallel and at the same time accurate failure diagnosis can be achieved while requiring similar test resources (tester memory and tester channels) as for a single core. The proposed pipelined architecture relies on forming nonlinear equations on a very limited number of output pins that compress the outputs from the identical cores and solve them off-chip to reproduce the failure information of each core. A very nice feature of the proposed scheme is that the number of observation pins required to achieve a desirable level of diagnostic resolution does not scale with the number of identical cores and can practically be kept constant.