DocumentCode :
3152158
Title :
Die-level adaptive test: Real-time test reordering and elimination
Author :
Gotkhindikar, K.R. ; Daasch, W.R. ; Butler, K.M. ; Carulli, J.M., Jr. ; Nahar, A.
Author_Institution :
Integrated Circuits Design & Test Lab., Portland State Univ., Portland, OR, USA
fYear :
2011
fDate :
20-22 Sept. 2011
Firstpage :
1
Lastpage :
10
Abstract :
This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.
Keywords :
Bayes methods; integrated circuit testing; Bayesian statistics; die-level adaptive test; integrated circuit products; real-time test elimination; real-time test reordering; size 65 nm; test contents; test fail rates; test flow; test time reductions; wafer sort test response data; Adaptation models; Bayesian methods; Monitoring; Monte Carlo methods; Real time systems; Semiconductor device modeling; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1089-3539
Print_ISBN :
978-1-4577-0153-5
Type :
conf
DOI :
10.1109/TEST.2011.6139173
Filename :
6139173
Link To Document :
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