Title :
Effects of analog multiplier offsets on on-chip learning
Author :
Choi, Y.-K. ; Ahn, K.H. ; Lee, S.Y.
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
Offsets inherent in analog circuits have been big obstacle in analog implementations of backpropagation algorithm. In this article the effects of analog multiplier offsets on on-chip learning are systematically analyzed. Offsets in a multiplier are mathematically modeled and incorporated into backpropagation learning equations. The deformed equations are investigated to show how the offsets degrade learning performance and under which conditions the neuron´s output fails to converge. Simulation results agree well with analytic calculations
Keywords :
analogue integrated circuits; analogue multipliers; backpropagation; neural chips; analog multiplier offsets; backpropagation algorithm; backpropagation learning equations; learning performance; on-chip learning; Analog circuits; Analytical models; Backpropagation algorithms; Cost function; Degradation; Equations; Hardware; Mathematical model; Neurons; Noise level;
Conference_Titel :
Neural Networks,1997., International Conference on
Conference_Location :
Houston, TX
Print_ISBN :
0-7803-4122-8
DOI :
10.1109/ICNN.1997.616149
