Magic´s Circuit Extractor

We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are a new algorithm based on corner-stitching, and its ability to extract cells incrementally. Because the extractor is incremental, typically only a few cells must be re-extracted when the layout changes. The extractor computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies.