Silicon Compilation of Gate Array Bases

Traditionally, the fixed base layers of a gate array product are manually designed and laid out, and the router database representing each array base is obtained by manual data entry. This paper describes a new application of silicon compiler technology for the automatic generation of gate array bases. The automatic generation of router databases is also described. The Gate Array Base Compiler allows several topological parameters to be varied, including 1) the number of rows and columns of gates, 2) the number and distribution of routing channels, and 3) the I/O sequence. The Router Model Generator supports multiple router database formats. Besides flexibility, advantages include quick development of new base arrays at low cost with high design reliability.