Abstract :
The following topics are dealt with: design for testability (DFT) for general analog; defect-oriented and power-aware ATPG; ATE feature set expansions and test cost reduction; board diagnosis and safe boundary scan testing;RF DFT and test cost reduction; self-testing and test compression techniques;BIST and fault tolerance for SRAM;defects in advanced technologies; pre-and post-silicon validation for microprocessor and NOCs; timing high-speed digital interfaces; timing and power-aware DFT; microprocessor testing ;DFT for complex SOCs;learning from data- diagnosis and data mining; advancing mixed-signal test;and stacked device test.
Keywords :
SRAM chips; analogue circuits; automatic test pattern generation; boundary scan testing; built-in self test; data mining; design for testability; electronic engineering computing; fault diagnosis; microprocessor chips; mixed analogue-digital integrated circuits; network-on-chip; printed circuits; system-on-chip; ATE feature set expansion; BIST; NOC; SRAM; advanced technology; board diagnosis; data diagnosis; data mining; defect oriented ATPG; design for testability; fault tolerance; general analog circuit; high speed digital interface; microprocessor testing; mixed signal test; postsilicon validation; power aware ATPG; power-aware DFT; presilicon validation; safe boundary scan testing; self testing technique; stacked device test; test compression technique; test cost reduction; timing-aware DFT;
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-0153-5
DOI :
10.1109/TEST.2011.6139201
