Modeling Switch-Level Simulation Using Data Flow

The complexity of simulating large circuits is a bottleneck in the design process. Considerable attention is being focused on using multiprocessing architectures to speed up simulation. In order to utilize these architectures one first needs to capture the parallelism inherent in the simulation process. This paper explores data flow graphs as a means of expressing the parallelism in switch-level simulation. These data flow graphs, when executed on general purpose or special purpose data flow machines should result in considerable speed up.