Design of antenna-configurable MIMO detector with high speed sorting architectures

In this paper, we propose an improved antenna-configurable MIMO detector combining with a high speed sorting architecture. The Codebook Enumeration (CBE) is applied to take advantages in multiple antenna configurations and signal modulations. The Parallel-Slice Merge Algorithm (PSMA) and Parallel Bubble-Slice Sort (PBSS) are also adopted to accelerate sorting speed. The proposed design applies pipelined architecture to speed up the operational frequency. Furthermore, Shift-Multiplier (SM) is also applied to reduce the critical timing path and circuit complexity. The proposed hardware circuit is realized in 90nm CMOS technology, and can operate at the maximum frequency 281MHz and the power consumption is 54.66mW.