Title :
Effect of NBTI degradation on transistor variability in advanced technologies
Author :
Pae, S. ; Maiz, J. ; Prasad, C.
Author_Institution :
Intel Corp., Hillsboro
Abstract :
The effect of PMOS Negative Bias Temperature Instability (NBTI) on product performance is a concern. As technology scales and device dimension shrinks, the trend in the Vt-variability at both time zero and after NBTI aging increases. The timeO Vt- variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the device aging-induced variability. This paper focuses on the NBTI-induced device Vt-variability and trend across technology generations. The remarkable correlation of aging-induced Vt-variability to the gate oxide area suggests that the geometry scaling is the dominant component that drives the increased trend in aging-induced variability.
Keywords :
MOSFET; circuit stability; semiconductor device reliability; device aging-induced variability; geometry scaling; negative bias temperature instability; transistor variability degradation; Aging; Degradation; Dielectrics; Geometry; Logic devices; Negative bias temperature instability; Niobium compounds; Random access memory; Titanium compounds; Transistors;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International
Conference_Location :
S. Lake Tahoe, CA
Print_ISBN :
978-1-4244-1771-9
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2007.4469214
