The Construction of Minimal Area Power and Ground Nets for VLSI Circuits

This paper deals with the problem of sizing power and ground nets in integrated circuits composed of modules, where the nets are routed in the channels between the modules. Constraints are assumed on allowable voltage drops between the chip´s power and ground pads and the module´s power and ground pins. Maximum current drain into each module is also assumed to be known. A procedure for determining the width of each branch in the power and ground trees is presented, where the objective is to minimize the area of the power and ground nets subject to several constraints, such as IR voltage drop and metal migration.