PLA Driver Selection: An Analytic Approach

Few integrated circuit design tools support the rapid exploration of the design space across performance alternatives. Such a tool must rely on extensive analysis of fundamental design issues, to provide the basis for this exploration. These detailed analyses are summarized as simple "rules-of-thumb." A more flexible class of design tools can use these to generate integrated circuit designs with more desirable performance. This paper describes the detailed analysis of the PLA driver selection problem. Rules-of-thumb which summerize these results for nMOS, are developed and applied to a large CPU design project currently underway at Berkeley. A maximum critical driver delay improvement of 46% was realized.