Optimized structure design for wafer level electromigration tests

Electromigration failure mode has been recognized as a strong limitation to scaling of copper interconnects for years. The development, as well as manufacturing monitoring, of advanced CMOS processes requires a large number of electromigration tests. Such industrial need is in favour of fast wafer level test rather than long-term tests on packaged samples. However, lifetimes issued from wafer level tests are still difficult to project to operating conditions since large uncertainties affect activation energy Ea and current density exponent n calculated using this methodology. Despite several improvements on the test procedure itself, longitudinal temperature gradients in metal line under test still represent a source of errors. Here, we present a characterization of thermal gradients developing in electromigration tests lines and a new design of test structure to minimize these gradients. By performing electromigration wafer level tests on this new structure, we observe a great improvement in Ea determination.