DocumentCode
3154017
Title
An interconnect interface for reconfigurable multimedia system
Author
Tan, Bo ; Liu, Leibo ; Yin, Shouyi ; Zhu, Min ; Jia, Wen ; Wei, Shaojun
Author_Institution
Res. Center for Mobile Comput., Tsinghua Univ., Beijing, China
fYear
2011
fDate
16-18 April 2011
Firstpage
4751
Lastpage
4754
Abstract
This paper propose an efficient interconnect interface, which has been applied in reconfigurable multimedia system (REMUS). In order to achieve high performance of data share between multi cores, this interconnect interface applies overlapping operation mechanism in memory. Test of H.264 HiP (High Profile) decoding shows that the data exchange rate achieves a speedup of 285% compared with the AHB external memory, and the decoding can achieve a speed up of 12.0%. With the support of this competitive work, REMUS could achieve 1080p@30fps of H.264 HiP decoding when it works at the frequency of 200 MHz. This work is tested on the platform of SOC designer 7.1.
Keywords
multimedia computing; multiprocessing systems; multiprocessor interconnection networks; system-on-chip; video coding; AHB external memory; H.264 HiP decoding; SOC designer; data exchange rate; frequency 200 MHz; interconnecting interface; reconfigurable multimedia system; video coding; Computer architecture; Decoding; Entropy; Integrated circuit interconnections; Multimedia communication; Streaming media; Interconnect interface; Overlapping operation; Reconfigurable multimedia system;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
Conference_Location
XianNing
Print_ISBN
978-1-61284-458-9
Type
conf
DOI
10.1109/CECNET.2011.5768526
Filename
5768526
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