DocumentCode
3154115
Title
Optimized reliability guardbands using variation aware junction temperature models
Author
Pereira, Paul ; Kim, Daniel ; O´Shea, Peter
Author_Institution
PMC-Sierra Inc., Santa Clara
fYear
2007
fDate
15-18 Oct. 2007
Firstpage
132
Lastpage
134
Abstract
Reliability guardbands for speed degradation are often based on a worst-case temperature condition. However, for 90 nm and 65 nm devices with non-negligible leakage, the junction temperatures at use-conditions may vary significantly between slow, marginal devices and fast devices. By accounting for this temperature variation it is possible to reduce the speed guardband and increase yield.
Keywords
process design; semiconductor device packaging; semiconductor device reliability; optimized reliability guardband; speed degradation; speed guardband reduction; temperature variation; variation aware junction temperature model; worst-case temperature condition; Bonding; Circuits; Equations; Frequency; Logic devices; Packaging; Power measurement; Temperature dependence; Thermal degradation; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International
Conference_Location
S. Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-1771-9
Electronic_ISBN
1930-8841
Type
conf
DOI
10.1109/IRWS.2007.4469239
Filename
4469239
Link To Document