DocumentCode
3154178
Title
Logic Synthesis and Optimization Benchmarks for the 1986 Design Automation Conference
Author
De Geus, Aart J.
Author_Institution
GE Calma Company, Research Triangle Park, NC
fYear
1986
fDate
29-2 June 1986
Firstpage
78
Lastpage
78
Abstract
In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.
Keywords
Acceleration; Availability; Circuit synthesis; Circuit testing; Design automation; Design optimization; Logic circuits; Logic design; Programmable logic arrays; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586071
Filename
1586071
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