Analysis of leakage power reduction techniques in digital circuits

With the advent of battery operated devices and scaling trends in deep submicron (DSM) regime, leakage power is becoming large component of total power dissipation. In this paper leakage reduction techniques viz. Stack forcing and Multi-Threshold CMOS (MTCMOS) have been implemented on CMOS, Complementary Pass Transistor Logic (CPL), and Transmission Gate (TG) logic style based digital circuits. The effects of these techniques are analysed and compared using NAND, MUX, XOR, and Full Adder circuits. MTCMOS approach showed significant leakage power reduction by the order of three in case of CMOS and modified TG logic style based circuits. MTCMOS approach was not effective in CPL style circuits as it was in CMOS and TG logic style circuits, in standby mode. In Stack forced approach, decent leakage power reduction is achieved with large delay overhead, for all CMOS, CPL and TG logic style based circuits. Designs and simulations were done on Cadence® Virtuoso® and Spectre® tools, using UMC 0.18 μm technology.