DocumentCode
3154384
Title
Low power, low area, high speed architectural design for motion estimation in MPEG-4
Author
Guhagarkar, Nikhil R. ; Shaik, Rafi Ahamed
Author_Institution
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
fYear
2011
fDate
16-18 Dec. 2011
Firstpage
1
Lastpage
4
Abstract
The key to high performance of MPEG-4 video compression lies in an efficient reduction of spatial and temporal redundancy. The main idea of inter prediction techniques is quick checking of the entire search area with efficient matching criterion viz. sum of absolute difference to eliminate the impossible or least matched candidates, followed by finer selection among the potentially best matched candidates. The macroblock with least SAD value will decide the motion vector. Due to object-based nature of MPEG-4, new SAD design with efficient computational ability, less area and less power in 0.18μm CMOS technology and operating frequency of 1.508GHz is proposed in the following paper.
Keywords
CMOS integrated circuits; UHF integrated circuits; data compression; image matching; low-power electronics; motion estimation; video coding; CMOS technology; MPEG-4 video compression; SAD value; computational ability; frequency 1.508 GHz; high speed architectural design; interprediction techniques; macroblock; matching criterion; motion estimation; motion vector; object-based nature; size 0.18 mum; spatial redundancy reduction; temporal redundancy reduction; Arrays; Motion estimation; Signal processing algorithms; Transform coding; Very large scale integration; SAD; VLSI architecture; block matching; integer motion estimation; macro block; motion estimation; systolic array;
fLanguage
English
Publisher
ieee
Conference_Titel
India Conference (INDICON), 2011 Annual IEEE
Conference_Location
Hyderabad
Print_ISBN
978-1-4577-1110-7
Type
conf
DOI
10.1109/INDCON.2011.6139380
Filename
6139380
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