DocumentCode
3154416
Title
SLS - A Fast Switch Level Simulator for Verification and Fault Coverage Analysis
Author
Barzilai, Z. ; Beece, D.K. ; Huisman, L.M. ; Iyengar, V.S. ; Silberman, G.M.
Author_Institution
IBM Watson Research Center, Yorktown Heights, NY
fYear
1986
fDate
29-2 June 1986
Firstpage
164
Lastpage
170
Abstract
We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.
Keywords
Analytical models; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Design automation; Discrete event simulation; Laser sintering; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586084
Filename
1586084
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