DocumentCode :
3154559
Title :
Reasoning about Digital Systems Using Temporal Logic
Author :
Bapat, S. ; Venkatesh, G.
Author_Institution :
Dept. of Computer Sc. & Engg., Indian Institute of Technology
fYear :
1986
fDate :
29-2 June 1986
Firstpage :
215
Lastpage :
219
Abstract :
Temporal logic is proposed as a medium to describe the timing behaviour of digital systems. Queries on the timing properties of the digital systems can then be answered by testing the satisfiability of appropriately constructed temporal formulae. We suggest ways of improving the standard tableau method of testing the satisfiability of these formulae, and discuss results obtained from an implementation of this method. We claim that this can serve as a designers assistant to debug designs.
Keywords :
Boolean algebra; Counting circuits; Design automation; Digital systems; Hardware; Logic functions; Solid state circuits; System testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1986. 23rd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0702-5
Type :
conf
DOI :
10.1109/DAC.1986.1586091
Filename :
1586091
Link To Document :
بازگشت