A Heuristic Chip-Level Test Generation Algorithm

An algorithm is given for generating tests from chip-level functional descriptions. The algorithm uses a chip-level fault model to define faults and fault sensitization requirements, and uses the hardware description language (HDL) definition to solve for the test vector. Artificial intelligence techniques of goal trees and rule databases are used to implement the algorithm in ProLog. The goal types and solving strategies are outlined. The current, partial ProLog implementation is discussed.