Integrated Placement/Routing in Sliced Layouts

An approach to simultaneous placement and routing of hierarchical IC layouts is presented. The method is based on the concept of slicing, which introduces a specific regularity to the problem at certain constraints on the chip floorplan. The placement part consists of a number of interrelated linear ordering problems, corresponding to the ordering problems, corresponding to the ordering of slices. The routing part outlines a hierarchical pattern router, applicable to slicing structures. The IC layout construction progresses top-down in small design increments, corresponding to processing of the individual slices. The placement and routing data are acquired at intervening time slots and influence each other on each hierarchy level.