DocumentCode
3154836
Title
Loop scheduling algorithm for timing and memory operation minimization with register constraint
Author
Chen, E. ; Tongsima, S. ; Sha, E.H.-M.
Author_Institution
Notre Dame Univ., IN, USA
fYear
1998
fDate
8-10 Oct 1998
Firstpage
579
Lastpage
588
Abstract
We present a novel scheduling framework, called memory operation minimization rotation scheduling (MORS), for scheduling multi-dimensional applications subject to register constraints and other resource constraints. Under such constraints, MORS strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure. Experiments show that our approach is useful for reducing the schedule length without violating the register constraint of a target machine. Furthermore, the average reduction in the schedule length produced by these experiments reaches 36.6%
Keywords
minimisation; processor scheduling; program control structures; storage management; timing; MORS; load operations; loop scheduling algorithm; memory operation minimization rotation scheduling; register constraint; store operations; timing; Application software; Digital signal processing; Flow graphs; Memory management; Minimization methods; Pipeline processing; Processor scheduling; Registers; Scheduling algorithm; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location
Cambridge, MA
ISSN
1520-6130
Print_ISBN
0-7803-4997-0
Type
conf
DOI
10.1109/SIPS.1998.715820
Filename
715820
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