DocumentCode
3155064
Title
Loop Scheduling Algorithm For Timing And Memory Operation Minimization With Register Constraint
Author
Chen, E. ; Tongsima, S. ; Sha, E.H.-M.
Author_Institution
University of Notre Dame
fYear
1998
fDate
10-10 Oct. 1998
Firstpage
579
Lastpage
588
Keywords
Minimization methods; Registers; Scheduling algorithm; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location
Cambridge, MA, USA
ISSN
1520-6130
Print_ISBN
0-7803-4997-0
Type
conf
DOI
10.1109/SIPS.1998.715821
Filename
715821
Link To Document