DocumentCode
3155165
Title
Vanguard: A Chip Physical Design System
Author
Hauge, Peter S. ; Yoffa, Ellen J.
Author_Institution
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
fYear
1986
fDate
29-2 June 1986
Firstpage
440
Lastpage
446
Abstract
Vanguard is a new physical design system which combines advantages of gate array and custom design methods to produce high-density chips on non-custom regular images. Vanguard physically partitions a chip into subchips which define macro boundaries and which contain not only macro circuitry and internal macro wires but also inter-macro connections and portions of connections which are part of the final chip design and lie within that region. Subchips are individually designed and then connected by abutment to assemble the chip. Vanguard has been used to design a 32-bit DCVS microprocessor comprising 13 macros, including a large register array.
Keywords
Assembly; Chip scale packaging; Circuits; Design automation; Design methodology; Pins; Registers; Switches; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586126
Filename
1586126
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