Title :
Optimal Order of the VLSI IC Testing Sequence
Author_Institution :
Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
Abstract :
In this paper we introduce a technique which manipulates the order of tests to minimize the length of the testing sequence. Probabilities of fault occurrences which are analyzed in terms of random phenomena inherent in VLSI manufacturing process are used to determine this optimal testing order. Simulation of the PLA testing process indicates that there exist possibilities for the significant improvement in testing efficiency of the actual VLSI circuit.
Keywords :
Acoustic testing; Automatic testing; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Manufacturing; Programmable logic arrays; Semiconductor device testing; Very large scale integration;
Conference_Titel :
Design Automation, 1986. 23rd Conference on
Print_ISBN :
0-8186-0702-5
DOI :
10.1109/DAC.1986.1586143
