DocumentCode
3155586
Title
HAL II: A Mixed Level Hardware Logic Simulation System
Author
Takasaki, Shigeru ; Sasaki, Tohru ; Nomizu, Nobuyoshi ; Ishikura, Hiroshi ; Koike, Nobuhiko
Author_Institution
NEC Corporation Tokyo, Japan
fYear
1986
fDate
29-2 June 1986
Firstpage
581
Lastpage
587
Abstract
This paper describes a mixed level hardware logic simulation system, called Hardware Logic Simulator II (HAL II). This paper first shows a HAL II simulation method. Then, it overviews HAL II hardware and software system configurations, simulation mechanism and estimates system performance. The HAL II system can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language). Finally, it discusses system applications and results. The paper also indicates that HAL II has been successfully used.
Keywords
Circuit simulation; Computational modeling; Computer simulation; Delay; Digital systems; Hardware; Large scale integration; Logic; Manufacturing; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586146
Filename
1586146
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