VLSI implementation of a copy network for a multicast ATM switch

Author

Derome, J. ; Al-Khalili, D. ; Rahman, M.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1994

fDate

25-28 Sep 1994

Firstpage

328

Abstract

This paper describes the VLSI implementation of a 16×16 copy network for a multicast ATM packet switch. The network is based on a non-blocking broadcast banyan network (BBN) which uses the Boolean interval splitting algorithm to replicate cells. The network preserves cell sequencing and has an overflow mechanism based on a fetch & add address generation scheme. The 16×16 copy network was implemented using NTE´s 1.2 μm CMOS technology. It achieved a typical simulation speed of 266 Mbps and fits in a 67 mm² die

Keywords

Boolean functions; CMOS digital integrated circuits; VLSI; asynchronous transfer mode; electronic switching systems; packet switching; shared memory systems; switching networks; 1.2 mum; 266 Mbit/s; Boolean interval splitting algorithm; CMOS technology; VLSI; cell replication; cell sequencing; copy network; fetch & add address generation scheme; multicast ATM switch; nonblocking BBN; nonblocking broadcast banyan network; overflow mechanism; packet switch; shared memory; simulation speed; Asynchronous transfer mode; Boolean functions; CMOS digital integrated circuits; Electronic switching systems; Multicast channels; Packet switching; Shared memory systems; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on

Conference_Location

Halifax, NS

Print_ISBN

0-7803-2416-1

Type

conf

DOI

10.1109/CCECE.1994.405755

Filename

405755