SRAM yield estimation in the early stage of the design cycle

This paper describes an early memory yield prediction model using a memory sensitive area model. The proposed sensitive area prediction model calculates the sensitive area of a memory block for a given process technology and memory capacity. The model is capable of predicting the yield of a memory block in the early design phase without the derailed knowledge of the physical layout. The use of such a model in the early design stage helps to improve product quality and to reduce cost