Title :
Comparisons of CMOS PLA and Polycell Representations of Control Logic
Author :
Gerveshi, Chuistine M.
Author_Institution :
AT&T Bell Laboratories, Murray Hill, NJ
Abstract :
A comparison of the area and speed characteristics of CMOS PLA and Polycell representations of various control logic blocks was carried out. Both types of layout were generated automatically, and were derived from the same high level logic description. The major objectives were to quantify the differences between the two types of circuit and to predict Polycell speed and circuit area from the PLA truth table. Both objectives were achieved. Polycell layout was shown to be a viable alternative to PLAs under certain circumstances.
Keywords :
Automatic control; Automatic logic units; CMOS logic circuits; CMOS technology; Design automation; Lighting control; Logic design; Power dissipation; Programmable logic arrays; Very large scale integration;
Conference_Titel :
Design Automation, 1986. 23rd Conference on
Print_ISBN :
0-8186-0702-5
DOI :
10.1109/DAC.1986.1586155