Comparisons of CMOS PLA and Polycell Representations of Control Logic

A comparison of the area and speed characteristics of CMOS PLA and Polycell representations of various control logic blocks was carried out. Both types of layout were generated automatically, and were derived from the same high level logic description. The major objectives were to quantify the differences between the two types of circuit and to predict Polycell speed and circuit area from the PLA truth table. Both objectives were achieved. Polycell layout was shown to be a viable alternative to PLAs under certain circumstances.