High-speed programmable counter design for PLL based on a delay partition technique

A high-speed programmable counter for PLL clock generator is presented. Compared with conventional approach, the design serves as a post-scale counter and has advanced clock shift ability to provide programmable phase shifting and duty cycle. The proposed counter is used to implement continuous division factors 2-32 at high frequency in a 0.13¿m low power CMOS process. A so called ¿delay partition¿ method is employed to further improve the counter´s speed. Based on the post layout simulation the counter is capable of operating up to 1.7GHz for a 1.5V supply voltage with 3.2mW power consumption.