DocumentCode
3155793
Title
Test Input Generation Using UML Sequence and State Machines Models
Author
Bandyopadhyay, Aritra ; Ghosh, Sudipto
Author_Institution
Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO
fYear
2009
fDate
1-4 April 2009
Firstpage
121
Lastpage
130
Abstract
We propose a novel testing approach that combines information from UML sequence models and state machine models. Current approaches that rely solely on sequence models do not consider the effects of the message path under test on the states of the participating objects. Dinh-Trong et al. proposed an approach to test input generation using information from class and sequence models.We extend their variable assignment graph (VAG) based approach to include information from state machine models. The extended VAG (EVAG) produces multiple execution paths representing the effects of the messages on the states of their target objects.We performed mutation analysis on the implementation of a video store system to demonstrate that our test inputs are more effective than those that cover only sequence diagram paths.
Keywords
Unified Modeling Language; finite state machines; program testing; UML sequence models; extended VAG; state machines models; test input generation; variable assignment graph; video store system; Collaborative work; Computer science; Genetic mutations; Knowledge engineering; Optimized production technology; Performance analysis; Performance evaluation; Software testing; System testing; Unified modeling language; class models; model-based testing; sequence models; state machine models; test input generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Testing Verification and Validation, 2009. ICST '09. International Conference on
Conference_Location
Denver, CO
Print_ISBN
978-1-4244-3775-7
Electronic_ISBN
978-0-7695-3601-9
Type
conf
DOI
10.1109/ICST.2009.23
Filename
4815344
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